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? semiconductor components industries, llc, 2013 august, 2013 ? rev. 5 1 publication order number: pca9306/d pca9306 dual bidirectional i 2 c-bus and smbus voltage-level translator the pca9306 is a dual bidirectional i 2 c ? bus and smbus voltage ? level translator with an enable (en) input. features ? 2 ? bit bidirectional translator for sda and scl lines in mixed ? mode i 2 c ? bus applications ? standard ? mode, fast ? mode, and fast ? mode plus i 2 c ? bus and smbus compatible ? less than 1.5 ns maximum propagation delay to accommodate standard ? mode and fast ? mode i 2 c ? bus devices and multiple masters ? allows voltage level translation between: ? 1.0 v v ref(1) and 1.8 v, 2.5 v, 3.3 v or 5 v v bias(ref)(2) ? 1.2 v v ref(1) and 1.8 v, 2.5 v, 3.3 v or 5 v v bias(ref)(2) ? 1.8 v v ref(1) and 3.3 v or 5 v v bias(ref)(2) ? 2.5 v v ref(1) and 5 v v bias(ref)(2) ? 3.3 v v ref(1) and 5 v v bias(ref)(2) ? provides bidirectional voltage translation with no direction pin ? low 3.5 on ? state connection between input and output ports provides less signal distortion ? open ? drain i 2 c ? bus i/o ports (scl1, sda1, scl2 and sda2) ? 5 v tolerant i 2 c ? bus i/o ports to support mixed ? mode signal operation ? high ? impedance scl1, sda1, scl2 and sda2 pins for en = low ? lock ? up free operation ? flow through pinout for ease of printed ? circuit board trace routing ? packages offered: ? tssop ? 8, us8, uqfn8, udfn8 ? esd performance: 4000 v human body model, 400 v machine model ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? these are pb ? free devices http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information marking diagrams tssop ? 8 dt suffix case 948al aaf yww a 1 8 1 8 ak m us8 us suffix case 493 1 8 uqfn8 mu suffix case 523an aq m 1 aaf, ak, aq, p = specific device code a = assembly location y = year ww = work week m = date code = pb ? free package udfn8 1.45 x 1.0 case 517bz p m 1
pca9306 http://onsemi.com 2 function description the pca9306 is a dual bidirectional i 2 c ? bus and smbus voltage ? level translator with an enable (en) input, and is operational from 1.0 v to 3.6 v (v ref(1) ) and 1.8 v to 5.5 v (v bias(ref)(2) ). the pca9306 allows bidirectional voltage translations between 1.0 v and 5 v without the use of a direction pin. the low on ? state resistance (r on ) of the switch allows connections to be made with minimal propagation delay. when en is high, the translator switch is on, and the scl1 and sda1 i/o are connected to the scl2 and sda2 i/o, respectively, allowing bidirectional data flow between ports. when en is low, the translator switch is off, and a high ? impedance state exists between ports. the pca9306 is not a bus buffer that provides both level translation and physical capacitance isolation to either side of the bus when both sides are connected. the pca9306 only isolates both sides when the device is disabled and provides voltage level translation when active. the pca9306 can be used to run two buses, one at 400 khz operating frequency and the other at 100 khz operating frequency. if the two buses are operating at different frequencies, the 100 khz bus must be isolated when the 400 khz operation of the other bus is required. if the master is running at 400 khz, the maximum system operating frequency may be less than 400 khz because of the delays added by the translator. as with the standard i 2 c ? bus system, pull ? up resistors are required to provide the logic high levels on the translator?s bus. the pca9306 has a standard open ? collector configuration of the i 2 c ? bus. the size of these pull ? up resistors depends on the system, but each side of the translator must have a pull ? up resistor. the device is designed to work with standard ? mode, fast ? mode and fast mode plus i 2 c ? bus devices in addition to smbus devices. the maximum frequency is dependent on the rc time constant, but generally supports > 2 mhz. when the sda1 or sda2 port is low, the clamp is in the on ? state and a low resistance connection exists between the sda1 and sda2 ports. assuming the higher voltage is on the sda2 port, when the sda2 port is high, the voltage on the sda1 port is limited to the voltage set by vref1. when the sda1 port is high, the sda2 port is pulled to the drain pull ? up supply voltage (v pu(d) ) by the pull ? up resistors. this functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. the scl1/scl2 channel also functions as the sda1/sda2 channel. all channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. this is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. the translator provides excellent esd protection to lower voltage devices, and at the same time protects less esd ? resistant devices. functional diagram figure 1. logic diagram
pca9306 http://onsemi.com 3 pin assignments figure 2. tssop ? 8 / us8 pinouts figure 3. uqfn8 pinout (top thru view) figure 4. udfn8 pinout (top thru view) table 1. pin description pin description gnd ground vref1 low ? voltage side reference supply voltage for scl1 and sda1 scl1 serial clock, low ? voltage side; connect to vref1 through a pull ? up resistor sda1 serial data, low ? voltage side; connect to vref1 through a pull ? up resistor sda2 serial data, high ? voltage side; connect to vref2 through a pull ? up resistor scl2 serial clock, high ? voltage side; connect to vref2 through a pull ? up resistor vref2 high ? voltage side reference supply voltage for scl2 and sda2 en switch enable input; connect to vref2 and pull ? up through a high resistor table 2. function table input en (note 1) function low disconnect high scl1 = scl2; sda1 = sda2 1. en is controlled by the v bias(ref)(2) logic levels and should be at least 1 v higher than v ref(1) for best translator operation.
pca9306 http://onsemi.com 4 table 3. maximum ratings symbol parameter value unit v ref(1) reference voltage (note 2) ? 0.5 to +7.0 v v bias(ref)(2) reference bias voltage (note 3) ? 0.5 to +7.0 v v in input voltage ? 0.5 to +7.0 v v i/o input / output pin voltage ? 0.5 to +7.0 v i ch dc channel current 128 ma i ik dc input diode current v in < gnd ? 50 ma t stg storage temperature range ? 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds t l = 260 c t j junction temperature under bias t j = 150 c ja thermal resistance (note 2) ja = 150 c/w p d power dissipation in still air at 85 c p d = 833 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in v esd esd withstand voltage human body mode (note 3) machine model (note 4) charged device model (note 5) > 4000 > 400 n/a v i latchup latchup performance above v cc and below gnd at 125 c (note 6) 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. measured with minimum pad spacing on an fr4 board, using 10 mm ? by ? 1 inch, 2 ounce copper trace no air flow. 3. tested to eia / jesd22 ? a114 ? a. 4. tested to eia / jesd22 ? a115 ? a. 5. tested to jesd22 ? c101 ? a. 6. tested to eia / jesd78. table 4. recommended operating conditions symbol parameter min max unit v ref(1) reference voltage (1) (note 7) vref1 0 5.5 v v bias(ref)(2) reference bias voltage (2) (note 7) vref2 0 5.5 v v i/o input / output pin voltage scl1, sda1, scl2, sda2 0 5.5 v v i(en) control pin input voltage en 0 5.5 v i sw(pass) pass switch current 0 64 ma t a operating free ? air temperature ? 55 +125 c 7. v (ref)(1) v bias(ref)(2) ? 1 v for best results in level shifting applications.
pca9306 http://onsemi.com 5 table 5. dc electrical characteristics symbol parameter conditions t a = ? 55 c to +125 c unit min typ (note 8) max v ik input clamping voltage i i = ? 18 ma; v i(en) = 0 v ? 1.2 v i ih high ? level input current v i = 5 v; v i(en) = 0 v 5 a c i(en) en pin input capacitance v i = 3 v or 0 v 7.1 pf c i/o(off) off ? state i/o pin capacitance scln, sdan v o = 3 v or 0 v; v i(en) = 0 v 4 6 pf c i/o(on) on ? state i/o pin capacitance scln, sdan v o = 3 v or 0 v; v i(en) = 3 v 9.3 12.5 pf r on on ? state resistance (2)(3) scln, sdan v i = 0 v; i o = 64 ma v i(en) = 4.5 v v i(en) = 3 v v i(en) = 2.3 v v i(en) = 1.5 v 2.4 3.0 3.8 9.0 5.0 6.0 8.0 20 v i = 2.4 v; i o = 15 ma v i(en) = 4.5 v v i(en) = 3 v 4.8 46 7.5 80 v i = 1.7 v; i o = 15 ma v i(en) = 2.3 v 40 80 8. all typical values are at t a = 25 c. 9. measured by the voltage drop between the scl1 and scl2, or sda1 and sda2 terminals at the indicated current through the switc h. on ? state resistance is determined by the lowest voltage of the two terminals. 10. guaranteed by design. table 6. ac electrical characteristics (translating down) ? values guaranteed by design symbol parameter test condition load condition t a = ? 55 c to +125 c unit min max see figure 4 load switch at s2 position t plh low ? to ? high propagation delay, from (input) scl2 or sda2 to (output) scl1 or sda1 v i(en) = 3.3 v; v ih = 3.3 v; v il = 0 v; v m = 1.15 v c l = 15 pf 0 0.6 ns c l = 30 pf 0 1.2 c l = 50 pf 0 2.0 t phl high ? to ? low propagation delay, from (input) scl2 or sda2 to (output) scl1 or sda1 c l = 15 pf 0 0.75 c l = 30 pf 0 1.5 c l = 50 pf 0 2.0 t plh low ? to ? high propagation delay, from (input) scl2 or sda2 to (output) scl1 or sda1 v i(en) = 2.5 v; v ih = 2.5 v; v il = 0 v; v m = 0.75 v c l = 15 pf 0 0.6 ns c l = 30 pf 0 1.2 c l = 50 pf 0 2.0 t phl high ? to ? low propagation delay, from (input) scl2 or sda2 to (output) scl1 or sda1 c l = 15 pf 0 0.75 c l = 30 pf 0 1.5 c l = 50 pf 0 2.5
pca9306 http://onsemi.com 6 table 7. ac electrical characteristics (translating up) ? values guaranteed by design symbol parameter test condition load condition t a = ? 55 c to +125 c unit min max see figure 4 load switch at s1 position t plh low ? to ? high propagation delay, from (input) scl1 or sda1 to (output) scl2 or sda2 v i(en) = 3.3 v; v ih = 2.3 v; v il = 0 v; v tt = 3.3 v; v m = 1.15 v r l = 300 , c l = 15 pf 0 0.5 ns r l = 300 , c l = 30 pf 0 1.0 r l = 300 , c l = 50 pf 0 1.75 t phl high ? to ? low propagation delay, from (input) scl1 or sda1 to (output) scl2 or sda2 r l = 300 , c l = 15 pf 0 0.8 r l = 300 , c l = 30 pf 0 1.65 r l = 300 , c l = 50 pf 0 2.75 t plh low ? to ? high propagation delay, from (input) scl1 or sda1 to (output) scl2 or sda2 v i(en) = 2.5 v; v ih = 1.5 v; v il = 0 v; v tt = 2.5 v; v m = 0.75 v r l = 300 , c l = 15 pf 0 0.5 ns r l = 300 , c l = 30 pf 0 1.0 r l = 300 , c l = 50 pf 0 1.75 t phl high ? to ? low propagation delay, from (input) scl1 or sda1 to (output) scl2 or sda2 r l = 300 , c l = 15 pf 0 1.0 r l = 300 , c l = 30 pf 0 2.0 r l = 300 , c l = 50 pf 0 3.3 a. load circuit b. timing diagram s1 = translating up; s2 = translating down. c l includes probe and jig capacitance. all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o = 50 ; t r 2 ns; t f 2 ns. the outputs are measured one at a time, with one transition per measurement. figure 5. load circuit for outputs from output under test input output r l c l s1 s2 (open) v tt v ih v il v oh v ol v m v m v m v m ordering information device package shipping ? pca9306dtr2g tssop ? 8 (pb ? free) 4000 / tape & reel pca9306amutcg uqfn ? 8 (pb ? free) 3000 / tape & reel PCA9306FMUTCG udfn8 (pb ? free) 3000 / tape & reel pca9306usg us8 (pb ? free) 3000 / tape & reel nlv9306usg* ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable.
pca9306 http://onsemi.com 7 application information 1. the applied voltages at v ref(1) and v pu(d) should be such that v bias(ref)(2) is at least 1 v higher than v ref(1) for best translator operation. figure 6. typical application (switch always enabled) scl1 sda1 vref1 gnd 3 4 vref2 1 6 5 scl2 sda2 8 sw sw pca9306 7 200 k scl gnd 2 scl sda gnd en i 2 c ? bus master i 2 c ? bus device sda r pu r pu r pu r pu v ref(1) = 1.8 v (note 1) v pu(d) = 3.3 v (note 1) v cc v cc 2. in the enabled mode, the applied enable voltage and the applied voltage at v ref(1) should be such that v bias(ref)(2) is at least 1 v higher than v ref(1) for best translator operation. figure 7. typical application (switch enable control) scl1 sda1 vref1 gnd 3 4 vref2 1 6 5 scl2 sda2 8 sw sw pca9306 7 200 k scl sda gnd 2 scl sda gnd v cc v cc v ref(1) = 1.8 v (note 2) v pu(d) = 3.3 v r pu r pu r pu r pu 3.3 v enable signal (note 2) en on off i 2 c ? bus master i 2 c ? bus device bidirectional translation for the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the en input must be connected to vref2 and both pins pulled to high side v pu(d) through a pull ? up resistor (typically 200 k ). this allows vref2 to regulate the en input. a filter capacitor on vref2 is recommended. the i 2 c ? bus master output can be totem ? pole or open ? drain (pull ? up resistors may be required) and the i 2 c ? bus device output can be totem ? pole or open ? drain (pull ? up resistors are required to pull the scl2 and sda2 outputs to v pu(d) ). however, if either output is totem ? pole, data must be unidirectional or the outputs must be 3 ? stateable and be controlled by some direction ? control mechanism to prevent high ? to ? low contentions in either direction. if both outputs are open ? drain, no direction control is needed. the reference supply voltage (v ref(1) ) is connected to the processor core power supply voltage. when vref2 is connected through a 200 k resistor to a 3.3 v to 5.5 v v pu(d) power supply, and v ref(1) is set between 1.0 v and (v pu(d) ? 1 v), the output of each scl1 and sda1 has a maximum output voltage equal to vref1, and the output of each scl2 and sda2 has a maximum output voltage equal to v pu(d) .
pca9306 http://onsemi.com 8 table 8. application operating conditions refer to figure 6. symbol parameter conditions min typ (1) max unit v bias(ref)(2) reference bias voltage (2) v ref(1) + 0.6 2.1 5 v v i(en) en pin input voltage v ref(1) + 0.6 2.1 5 v v ref(1) reference voltage (1) 0 1.5 4.4 v i sw(pass) pass switch current 14 ma i ref reference current transistor 5 a t amb ambient temperature operating in free ? air ? 55 +125 c 11. all typical values are at t amb = 25 c. sizing pull ? up resistor the pull ? up resistor value needs to limit the current through the pass transistor when it is in the on state to about 15 ma. this ensures a pass voltage of 260 mv to 350 mv. if the current through the pass transistor is higher than 15 ma, the pass voltage also is higher in the on state. to set the current through each pass transistor at 15 ma, the pull ? up resistor value is calculated as: r pu v pu(d) 0.35 v 0.015 a (eq. 1) the following table summarizes resistor reference voltages and currents at 15 ma, 10 ma, and 3 ma. the resistor values shown in the +10% column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mv or less. the external driver must be able to sink the total current from the resistors on both sides of the pca9306 device at 0.175 v, although the 15 ma only applies to current flowing through the pca9306 device. table 9. pullup resistor values calculated for v ol = 0.35 v; assumes output driver v ol = 0.175 v at stated current. v pu(d) pullup resistor value ( ) 15 ma 10 ma 3 ma nominal +10% (note 12) nominal +10% (1) nominal +10% (note 12) 5 v 310 341 465 512 1550 1705 3.3 v 197 217 295 325 983 1082 2.5 v 143 158 215 237 717 788 1.8 v 97 106 145 160 483 532 1.5 v 77 85 115 127 383 422 1.2 v 57 63 85 94 283 312 12. +10% to compensate for v cc range and resistor tolerance. maximum frequency calculation the maximum frequency is totally dependent upon the specifics of the application and the device can operate > 33 mhz. basically, the pca9306 behaves like a wire with the additional characteristics of transistor device physics and should be capable of performing at higher frequencies if used correctly. here are some guidelines to follow that will help maximize the performance of the device: ? keep trace length to a minimum by placing the pca9306 close to the processor. ? the trace length should be less than half the time of flight to reduce ringing and reflections. ? the faster the edge of the signal, the higher the chance for ringing. ? the higher the drive strength (up to 15 ma), the higher the frequency the device can use. in a 3.3 v to 1.8 v direction level shift, if the 3.3 v side is being driven by a totem pole type driver no pull ? up resistor is needed on the 3.3 v side. the capacitance and line length of concern is on the 1.8 v side since it is driven through the on resistance of the pca9306. if the line length on the 1.8 v side is long enough there can be a reflection at the chip/terminating end of the wire when the transition time is shorter than the time of flight of the wire because the pca9306 looks like a high ? impedance compared to the wire. if the wire is not too long and the lumped capacitance is not excessive the signal will only be slightly degraded by the series resistance added by passing through the pca9306. if the lumped capacitance is large the rise time will deteriorate, the fall time is much less affected and if the rise time is slowed down too much the duty cycle of the clock will be degraded and at some point the clock will no longer be useful. so the principle design consideration is to minimize the wire length and the capacitance on the 1.8 v side for the clock path. a pull ? up resistor on the 1.8 v side can also be used to trade a slower fall time for a faster rise time and can also reduce the overshoot in some cases.
pca9306 http://onsemi.com 9 package dimensions tssop8, 4.4x3 case 948al issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
pca9306 http://onsemi.com 10 package dimensions us8 case 493 ? 02 issue b dim a min max min max inches 1.90 2.10 0.075 0.083 millimeters b 2.20 2.40 0.087 0.094 c 0.60 0.90 0.024 0.035 d 0.17 0.25 0.007 0.010 f 0.20 0.35 0.008 0.014 g 0.50 bsc 0.020 bsc h 0.40 ref 0.016 ref j 0.10 0.18 0.004 0.007 k 0.00 0.10 0.000 0.004 l 3.00 3.20 0.118 0.126 m 0 6 0 6 n 5 10 5 10 p 0.23 0.34 0.010 0.013 r 0.23 0.33 0.009 0.013 s 0.37 0.47 0.015 0.019 u 0.60 0.80 0.024 0.031 v 0.12 bsc 0.005 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension ?a? does not include mold flash, protrusion or gate burr. mold flash. protrusion and gate burr shall not exceed 0.140 mm (0.0055?) per side. 4. dimension ?b? does not include inter ? lead flash or protrusion. inter ? lead flash and protrusion shall not e3xceed 0.140 (0.0055?) per side. 5. lead finish is solder plating with thickness of 0.0076 ? 0.0203 mm. (300 ? 800 ?). 6. all tolerance unless otherwise specified 0.0508 (0.0002 ?). l b a p g 4 1 5 8 c k d seating j s r u detail e v f h n r 0.10 typ m ? y ? ? x ? ? t ? detail e t m 0.10 (0.004) xy t 0.10 (0.004) plane *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* mm inches scale 8:1 3.8 0.15 0.50 0.0197 1.0 0.0394 0.30 0.012 1.8 0.07
pca9306 http://onsemi.com 11 package dimensions case 523an issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. a b e d bottom view b e 8x 0.10 b 0.05 a c c note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 1 3 5 8 dim min max millimeters a 0.45 0.60 a1 0.00 0.05 a3 0.13 ref b 0.15 0.25 d 1.60 bsc l1 ??? 0.15 e 1.60 bsc e 0.50 bsc l 0.35 0.45 l1 detail a ?? *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* pitch 0.35 7x dimensions: millimeters 1 7 l3 0.25 1.70 1.70 0.50 l3 0.25 0.35 l3 (0.10) (0.15) 8x 0.53 8x 0.53 8x
pca9306 http://onsemi.com 12 package dimensions case 517bz issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.20 mm from terminal tip. 4. package dimensions exclusive of burrs and mold flash. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended dim min max millimeters a 0.45 0.55 a1 0.00 0.05 a3 0.13 ref b 0.15 0.25 d 1.45 bsc e 1.00 bsc e 0.35 bsc l 0.25 0.35 l1 0.30 0.40 a b e d 0.10 c pin one reference top view 0.10 c a a1 0.05 c 0.05 c c seating plane side view 2x 2x a3 bottom view b e 8x l 7x l1 1 4 5 8 e/2 dimensions: millimeters 0.22 7x 0.48 8x 1.18 0.53 pitch 0.35 1 pkg outline 0.10 b 0.05 a c c note 3 m m on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 pca9306/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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